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CS101 Fiches technique(PDF) 8 Page - Fujitsu Component Limited.

No de pièce CS101
Description  Standard Cell
Download  12 Pages
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Fabricant  FUJITSU [Fujitsu Component Limited.]
Site Internet  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

CS101 Fiches technique(HTML) 8 Page - Fujitsu Component Limited.

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CS101 Series
8
■ AC CHARACTERISTICS
*1 : Delay time = propagation delay time, enable time, disable time
*2 : “typ” is calculated based on the cell specifications.
*3 : Measurement condition
Note : The values are reference values, which vary depending on the cells.
■ I/O PIN CAPACITANCE
Note : The capacitance values vary depending on the package and pin positions.
■ DESIGN METHODS
Fujitsu Microelectronics’s Reference Design Flow provides the following functions that help shorten the devel-
opment time of large scale and high quality LSIs.
• High reliability design estimation in the early stage of physical design realized by physical prototyping.
• Layout synthesis with optimized timing realized by physical synthesis tools.
• High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and
crosstalk.
• I/O design environment (power line design, assignment and selection of I/Os, package selection) considering
noise.
■ PACKAGES
Packages available for existing series can be used for CS101 series. This allows smooth replacement with
previously developed products.
Please contact your Fujitsu Microelectronics agent for details of delivery times.
FBGA package
: Max 424 pins
FC-BGA package : Max 2116 pins
PBGA package
: Max 420 pins
TEBGA package
: Max 900 pins
(Packages under planning are included.)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Delay time
tpd *1
typ *2
× tmin *3
typ *2
× ttyp *3
typ *2
× tmax *3
ns
Measurement condition
tmin
ttyp
tmax
VDD
= 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to +125 °C
0.621.001.57
Parameter
Symbol
Value
Unit
Input pin
CIN
Max16
pF
Output pin
COUT
Max16
pF
I/O pin
CI/O
Max16
pF


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