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TSB43DB42GHC Fiches technique(PDF) 1 Page - Texas Instruments

No de pièce TSB43DB42GHC
Description  IEEE 1394a-2000 CONSUMER ELECTRONICS SOLUTION
Download  7 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TSB43DB42GHC Fiches technique(HTML) 1 Page - Texas Instruments

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FEATURES
TSB43DA42, TSB43DB42
SLLS560 – FEBRUARY 2007
IEEE 1394a-2000 CONSUMER ELECTRONICS SOLUTION
• 1394 Features
SRAM-Like 16-Bit Asynchronous Interface
(Supports External DMA Only)
Integrated 400/200/100 Mbps 2-Port PHY
PCI Interface (33 MHz) Compliant to PCI
Compliant to IEEE 1394-1995 and IEEE
Specification Version 2.2 (Supports PCI
1394a-2000 Standards
Slave and Master Function)
Supports Bus Manager Functions and
• Data Buffers
Automatic 1394 Self-ID Verification
3x 4K Byte Isochronous Buffers for Audio
Separate Asyncchronous Ack FIFOs
and Video Data
Decrease the Ack-Tracking Burden on
External CPU
2x 2K Byte Asynchronous/Asynchronous
Stream Transmit Buffers
• DTLA Encryption Support for MPEG2-DVB,
DSS, and Audio Data (TSB43DA42 Only)
2x 2K Byte Asynchronous/Asynchronous
Stream Receive Buffers
Support for up to Three
Encrypted/Decrypted Streams at One Time
1x 1K Byte Self-ID Buffer
Full Ake Performed With Hardware Assist
Insertion Buffers for MPEG2 Packet
Insertion (DAT, PMT, SIT, and DIT)
Secure Method for Loading DTLA
Information Using Ex-CPU Interface
Programmable Data/Space Available
Indicators for Buffer Flow Control
• Audio and Video Interfaces
• Hardware Packet Formatting for the Following
Three Configurable High-Speed Data Ports
Standards
for Video Data
IEC61883-1 (General)
Two Ports Configurable as Parallel or
Serial
IEC61883-2 (SD-DVCR)
One Port Serial Only
IEC61883-4 (MPEG2-TS)
Two Interfaces for Audio Data (Only One
IEC61883-6 (Audio and Music)
Audio Stream Supported at a Time)
IEC61883-7 (ITU-R BO.1294 System B) –
60958 Port
DSS
I2S-Style DAC Interface for PCM Data
Asynchronous Packets
(Two Channel)
Asynchronous Streams
Pass-Through Modes for HSDI0 and HSDI1
PHY Packets (Including Self-IDs)
Packet Insertion – Two Insertion Buffers
• Additional Features
per HSDI
JTAG Interface to Support Post-Assembly
PID Filtering (32 PID Filters per HSDI Port)
Scan of Device I/O – Boundary Scan
• External CPU Interfaces
Unique Binding Method for Protecting
Motorola 68K-Style 16-Bit Asynchronous
Sensitive Off-Chip Data From Ex-CPU
Interface (Supports External DMA Only)
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS
OTHERWISE
NOTED
this
document
contains
Copyright © 2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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