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TPS61182RTER Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce TPS61182RTER
Description  WLED DRIVER FOR NOTEBOOK DISPLAY
Download  26 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS61182RTER Fiches technique(HTML) 4 Page - Texas Instruments

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FUNCTIONAL BLOCK DIAGRAM
C2
4.7 F
m
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
VO
SW
PGND
GND
10 WLEDinseries,120 mA total
Current
Regulator
Dimming
Control
L1
10 H
m
Q1
D2
Cin
C4
0.1 F
m
Optional
CurrentMode
PWMControl
IFB 1... IFB 6
Fault
Protection
5 Vto 24 V
C1
4.7 F
m
R3
51 W
C3
1 F
m
InternalRegulator
(TPS61181/2only)
EN
PWMDimming
Fault
ISET
VBAT
EN
DCTRL
D1
R1
R3
100kW
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS61180/1/2
SLVS801A – DECEMBER 2007 – REVISED MARCH 2008
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
Voltages on pin VBAT and Fault
(2)
–0.3 to 24
V
Voltage on pin Cin(2)
–0.3 to 3.6
V
Voltage on pin SW and VO
(2)
–0.3 to 40
V
Voltage on pin IFB1 to IFB6(2)
–0.3 to 20
V
Voltage on all other pins (2)
–0.3 to 7
V
Continuous power dissipation
See Dissipation Rating Table
Operating junction temperature range
–40 to 150
°C
Storage temperature range
–65 to 150
°C
Lead temperature (soldering, 10 sec)
260
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to network ground terminal.
PACKAGE
RθJA
TA ≤ 25°C
TA = 70°C
TA = 85°C
POWER RATING
POWER RATING
POWER RATING
TPS61180/1/2RTE(1)
270
°C/W
370 mW
204 mW
148 mW
TPS61180/1/2RTE(2)
48.7
°C/W
2.05 W
1.13 W
821 mW
(1)
The JEDEC low-K (1s) board used to derive this data was a 3in
×3in, two-layer board with 2-ounce copper traces on top of the board.
(2)
The JEDEC high-K (2s2p) board used to derive this data was a 3in
×3in, multilayer board with 1-ounce internal power and ground.
4
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61180/1/2


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