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M27C516-35N6TR Fiches technique(PDF) 8 Page - STMicroelectronics |
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M27C516-35N6TR Fiches technique(HTML) 8 Page - STMicroelectronics |
8 / 12 page tAVPL VALID AI00936 A0-A14 Q0-Q15 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY Figure 6. Programming and Verify Modes AC Waveforms AI00707C n= 0 Last Addr VERIFY P = 100 µs Pulse ++n =25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL WORDS 1st: VCC =6V 2nd: VCC = 4.2V YES NO YES NO YES NO Figure 7. Programming Flowchart PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows to pro- gram the whole array with a guaranteedmargin, in a typical time of 3 seconds. Programming with PRESTO II involves the application of a sequence of 100 µs programpulses to each byteuntil a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C516s in parallelwith different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C516 may be common. A TTL low level pulse applied to a M27C516’s P input, with E low and VPP at 12.75V,will program that M27C516. A high level E input inhibits the other M27C516s from being programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH,VPP at 12.75V and VCC at 6.25V. 8/12 M27C516 |
Numéro de pièce similaire - M27C516-35N6TR |
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Description similaire - M27C516-35N6TR |
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