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M27W101-80F6TR Fiches technique(PDF) 8 Page - STMicroelectronics

No de pièce M27W101-80F6TR
Description  1 Mbit 128Kb x8 Low Voltage UV EPROM and OTP EPROM
Download  15 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M27W101-80F6TR Fiches technique(HTML) 8 Page - STMicroelectronics

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Figure 7. Programming Flowchart
AI00715D
n= 0
Last
Addr
VERIFY
P = 100
µs Pulse
++n
=25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC =5V
2nd: VCC = 2.7V
YES
NO
YES
NO
YES
NO
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed, with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II involves in applying a se-
quence of 100
µs program pulses to each byte until
a correct verify occurs (see Figure 7). During pro-
gramming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE at VCC much higher than
3.6V, provides necessary margin to each pro-
grammed cell.
Program Inhibit
Programming of multiple M27W101s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27W101 may be common. A TTL low level pulse
applied to a M27W101’s P input, with E low and
VPP at 12.75V, will program that M27W101. A high
level E input inhibits the other M27W101s from be-
ing programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at VIL, P at VIH,VPP at 12.75V and VCC at
6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00714
A0-A16
Q0-Q7
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY


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