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AD7357BRUZ-500RL7 Fiches technique(PDF) 7 Page - Analog Devices |
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AD7357BRUZ-500RL7 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 17 page Preliminary Technical Data AD7357 Rev. PrD | Page 7 of 17 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 12 13 14 15 16 11 10 9 VINA- REFA REFGND VINB- REFB AGND VINA+ SCLK SDATAA SDATAB CS AGND DGND VINB+ VDD VDRIVE AD7357 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 9 VDD Power Supply Input. The VDD range for the AD7357 is 2.5V +/- 5%. The supply should be decoupled to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor. 16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD. 10 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7357 and framing the serial data transfer. 15 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This clock is also used as the clock source for the conversion process. 14,13 SDATAA, SDATAB Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of one leading zero followed by the 14 bits of conversion data followed by a trailing zero. The data is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two further trailing zeros will appear after the 14 bits of data. If CS is held low for a further 18 SCLK cycles on either SDATAA or SDATAB , the data from the other ADC follows on the SDATA pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB. 12 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 5, 11 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input signals and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 4 REFGND Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. 3, 6 REFA, REFB Reference decoupling capacitor pins. Decoupling capacitors are connected between these pins and the REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple the each reference pin with a 10µF capacitor. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048V and this appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048+100mV to Vdd. 1, 2 VINA-, VINA+ Analog Inputs of ADC A. These analog inputs form a fully differential pair. 8, 7 VINB-, VINB+ Analog Inputs of ADC B. These analog inputs form a fully differential pair. |
Numéro de pièce similaire - AD7357BRUZ-500RL7 |
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Description similaire - AD7357BRUZ-500RL7 |
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