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W312-02 Fiches technique(PDF) 6 Page - SpectraLinear Inc

No de pièce W312-02
Description  FTG for VIA™ K7 Series Chipset with Programmable Output Frequency
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Fabricant  SPECTRALINEAR [SpectraLinear Inc]
Site Internet  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

W312-02 Fiches technique(HTML) 6 Page - SpectraLinear Inc

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W312-02
Rev 1.0, November 27, 2006
Page 6 of 19
W312-02 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
Spread Enable
0
0 = Disabled
1 = Enabled
Bit 6
Spread Select2
0
‘000’ = ±0.25%
‘001’ = –0.5%
‘010’ = ±0.5%
‘011’ = ±0.38%
‘100’ = Reserved
‘101’ = Reserved
‘110’ = Reserved
‘111’ = Reserved
Bit 5
Spread Select1
0
Bit 4
Spread Select0
0
Bit 3
SEL3
0
SW Frequency selection bits. See Table 5.
Bit 2
SEL2
0
Bit 1
SEL1
0
Bit 0
SEL0
0
Byte 1: Control Register 1
Bit
Pin#
Name
Default
Description
Bit 7
42, 41
CPUT0, CPUC0
1
(Active/Inactive)
Bit 6
39, 38
CPUT_CS,
CPUC_CS
1
(Active/Inactive)
Bit 5
6
48MHz
1
(Active/Inactive)
Bit 4
7
24_48MHz
1
(Active/Inactive)
Bit 3
Reserved
0
Reserved
Bit 2
28
AGP2
1
(Active/Inactive)
Bit 1
27
AGP1
1
(Active/Inactive)
Bit 0
26
AGP0
1
(Active/Inactive)
Byte 2: Control Register 2
Bit
Pin#
Name
Default
Description
Bit 7
20
PCI7
1
(Active/Inactive)
Bit 6
18
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
16
PCI4
1
(Active/Inactive)
Bit 3
14
PCI3
1
(Active/Inactive)
Bit 2
13
PCI2
1
(Active/Inactive)
Bit 1
11
PCI1
1
(Active/Inactive)
Bit 0
10
PCI0
1
(Active/Inactive)


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