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W312-02 Fiches technique(PDF) 1 Page - SpectraLinear Inc

No de pièce W312-02
Description  FTG for VIA™ K7 Series Chipset with Programmable Output Frequency
Download  19 Pages
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Fabricant  SPECTRALINEAR [SpectraLinear Inc]
Site Internet  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

W312-02 Fiches technique(HTML) 1 Page - SpectraLinear Inc

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FTG for VIA™ K7 Series Chipset
with Programmable Output Frequency
W312-02
Rev 1.0, November 27, 2006
Page 1 of 19
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
Features
• Single chip FTG solution for VIA™ K7 Series chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when watchdog timer
time-out
• Capable of generate system RESET after a watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for PCI output clocks
• Programmable output skew between CPU, AGP and PCI
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Two pairs of differential CPU clocks
• Eleven copies of PCI clocks
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• Three copies of 14.31818-MHz reference clocks
• One RESET output for system recovery
• Power management control support
Key Specifications
CPU Outputs Cycle-to-cycle Jitter: ............................. 250 ps
48-MHz, 3V66, PCI Outputs
Cycle-to-cycle Jitter: .................................................... 500 ps
CPU, 3V66 Output Skew: ............................................ 200 ps
48-MHz Output Skew: ................................................. 250 ps
PCI Output Skew: ........................................................ 500 ps
Block Diagram
Pin Configuration
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. De-
sign should not rely solely on internal pull-up resistor to set I/O pins
HIGH.
[1]
VDD_REF
VDD_CPU
PCI1:8
XTAL
PLL REF FREQ
PLL 1
X2
X1
REF2
24_48MHz/FS4*
PLL2
OSC
VDD_48MHz
SMBus
SDATA
Logic
SCLK
AGP0:2
CPUT0,CPUC0
CPUT_CS,CPUC_CS
Divider,
Delay,
and
Phase
Control
Logic
3
VDD_PCI
2
RST#
PCI0/SEL24_48#*
PCI9_E
/2
(FS0:4)
5
48MHz/FS3*
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS2/48MHz
*FS3/24_48MHz
GND_48MHz
*FS4/PCI_F
*SEL24_48#/PCI0
PCI1
GND_PCI
PCI2
PCI3
VDD_PCI
PCI4
PCI5
PCI6
GND_PCI
PCI7
PCI8
PCI9_E
VDD_PCI
RST#
REF0/FS0*
REF1/FS1*
REF2
REF_STOP#*
AGP_STOP#*
GND_CPU
CPUT0
CPUC0
VDD_CPU
CPUT_CS
CPUC_CS
GND_CPU
CPU_STOP#*
PCI_STOP#*
PD#*
VDD_CORE
GND_CORE
SDATA
SCLK
GND_AGP
AGP2
AGP1
AGP0
VDD_AGP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1/FS1*
REF0/FS0*
VDD_AGP
SEL24_48#*
PD#
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#


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