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MC100ES6254FA Fiches technique(PDF) 3 Page - Integrated Device Technology

No de pièce MC100ES6254FA
Description  2.5/3.3V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

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MC100ES6254/D
TIMING SOLUTIONS
3
a.
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 1. PIN CONFIGURATION
Pin
I/O
Type
Function
CLK0, CLK0
Input
LVPECL
Differential reference clock signal input 0
CLK1, CLK1
Input
LVPECL
Differential reference clock signal input 1
OEA, OEB
Input
LVCMOS
Output enable
SEL0, SEL1
Input
LVCMOS
Clock switch select
QA[0-2], QA[0-2]
QB[0-2], QB[0-2]
Output
LVPECL
Differential clock outputs (banks A and B)
GND
Supply
GND
Negative power supply
VCC
Supply
VCC
Positive power supply. All VCC pins must be connected to the positive power supply for correct
DC and AC operation
Table 2. FUNCTION TABLE
Control
Default
0
1
OEA
0
QA[0-2], Qx[0-2] are active. Deassertion of OE can be
asynchronous to the reference clock without generation
of output runt pulses
QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion
of OE can be asynchronous to the reference clock
without generation of output runt pulses
OEB
0
QA[0-2], Qx[0-2] are active. Deassertion of OE can be
asynchronous to the reference clock without generation
of output runt pulses
QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion
of OE can be asynchronous to the reference clock
without generation of output runt pulses
SEL0, SEL1
00
Refer to Table 3
Table 3. CLOCK SELECT CONTROL
SEL0
SEL1
CLK0 routed to
CLK1 routed to
Application Mode
0
0
QA[0:2] and QB[0:2]
---
1:6 fanout of CLK0
0
1
---
QA[0:2] and QB[0:2]
1:6 fanout of CLK1
1
0
QA[0:2]
QB[0:2]
Dual 1:3 buffer
1
1
QB[0:2]
QA[0:2]
Dual 1:3 buffer (crossed)
Table 4. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
-0.3
3.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
VOUT
DC Output Voltage
-0.3
VCC+0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage temperature
-65
125
°C
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC100ES6254
2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
NETCOM
IDT™ 2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6254
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