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CDCU877BZQLT Fiches technique(PDF) 11 Page - Seme LAB |
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CDCU877BZQLT Fiches technique(HTML) 11 Page - Seme LAB |
11 / 17 page www.ti.com RECOMMENDED AVDD FILTERING V DDQ GND CARD VIA CARD VIA Bead 0603 4.7 F m 1206 0.1 F m 0603 2200pF 0603 AV DD AGND PLL 1 W CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS801B – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 11. Time Delay Between OE and Clock Output (Y, Y) A. Place the 2200-pF capacitor close to the PLL. B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz). Figure 12. Recommended AVDD Filtering 11 Submit Documentation Feedback |
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