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ST72F321BR6T6 Fiches technique(PDF) 7 Page - STMicroelectronics |
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ST72F321BR6T6 Fiches technique(HTML) 7 Page - STMicroelectronics |
7 / 187 page 7/187 1 DESCRIPTION The ST72F321B Flash and ST72321B ROM de- vices are members of the ST7 microcontroller fam- ily designed for mid-range applications. All devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set and are available with Flash or ROM pro- gram memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The on-chip peripherals include an A/D converter, a PWM Autoreload timer, 2 general purpose tim- ers, I2C bus, SPI interface and an SCI interface. For power economy, microcontroller can switch dynamically into WAIT, SLOW, ACTIVE-HALT or HALT mode when the application is in idle or stand-by state. Typical applications are consumer, home, office and industrial products. Related Documentation AN1131: Migrating applications from ST72511/ 311/314 to ST72521/321/324 Figure 1. Device Block Diagram 8-BIT CORE ALU OSC1 VPP CONTROL PROGRAM (32K - 60K Bytes) VDD RESET PORT F PF7:0 (8-bits) TIMER A BEEP PORT A RAM (1024 - 2048 Bytes) PORT C 10-BIT ADC VAREF VSSA PORT B PB7:0 (8-bits) PWM ART PORT E PE7:0 (8-bits) SCI TIMER B PA7:0 (8-bits) PORT D PD7:0 (8-bits) SPI PC7:0 (8-bits) VSS WATCHDOG TLI OSC LVD OSC2 MEMORY MCC/RTC/BEEP EVD AVD I2C |
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