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AD5066BRUZ-1REEL7 Fiches technique(PDF) 6 Page - Analog Devices

No de pièce AD5066BRUZ-1REEL7
Description  Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5066BRUZ-1REEL7 Fiches technique(HTML) 6 Page - Analog Devices

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AD5066
Preliminary Technical Data
Rev. PrB | Page 6 of 20
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
t11
20
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
16.5
ns min
SYNC to SCLK falling edge set-up time
t5
5
ns min
Data set-up time
t6
5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
1.9
us min
Minimum SYNC high time (single channel update)
t8
10.5
us min
Minimum SYNC high time ( all channel update)
t9
16.5
ns min
SYNC rising edge to SCLK fall ignore
t10
0
ns min
SCLK falling edge to SYNC fall ignore
t11
20
ns min
LDAC pulse width low
t12
20
ns min
SCLK falling edge to LDAC rising edge
t13
10
ns min
CLR pulse width low
t14
10
ns min
SCLK falling edge to LDAC falling edge
t15
10.6
us min
CLR pulse activation time
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2mA
IOL
2mA
IOH
VOH (MIN)
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications


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