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GS1582-IBE3 Fiches technique(PDF) 10 Page - Gennum Corporation

No de pièce GS1582-IBE3
Description  Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner?
Download  114 Pages
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Fabricant  GENNUM [Gennum Corporation]
Site Internet  http://www.gennum.com
Logo GENNUM - Gennum Corporation

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GS1582 Data Sheet
40117 - 1 November 2007
10 of 114
B4
PCLK
Input
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode
PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
B5, C5, D5,
E2, E5, E6,
E7, F5, F6,
F7, G9, J8
CORE_GND
Non
Synchronous
Input
Power
Ground connection for the digital core logic. Connect to digital GND.
C6, C7, C8
PD_GND
Analog
Input
Power
Ground connection for the phase detector. Connect to analog GND.
B7
CP_RES
Input
Charge pump current setting resistor.
B8, B9
VCO_GND
Analog
Output
Power
Ground pins for the VCO.
B10
CP_GND
Analog
Input
Power
Ground pin for the charge pump and PLL.
C4
V/VSYNC
Synchronous
with PCLK
Input
PARALLEL DATA TIMING
Signal levels are LVCMOS/LVTTL compatible.
TIM_861 = LOW:
The V signal is used to indicate the portion of the video field/frame that
is used for vertical blanking, when DETECT_TRS is set LOW.
The V signal should be set HIGH for the entire vertical blanking period
and should be set LOW for all lines outside of the vertical blanking
interval.
The V signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The VSYNC signal indicates vertical timing. See Section 4.3.1 for timing
details.
The VSYNC signal is ignored when DETECT_TRS = HIGH.
C9, D9, E9,
F9
CD_GND
Analog
Input
Power
Ground connection for the serial digital cable driver. Connect to analog
GND.
C10, D10
SDO, SDO
Analog
Output
Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or
270Mb/s.
The slew rate of these outputs is automatically controlled to meet
SMPTE 292M and 259M requirements according to the setting of the
SD/HD pin.
Serial digital output signal from the internal cable driver.
NOTE: The SDO/SDO output signals will be set to high impedance
when RESET = LOW.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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