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TC94A39FB Fiches technique(PDF) 9 Page - Toshiba Semiconductor |
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TC94A39FB Fiches technique(HTML) 9 Page - Toshiba Semiconductor |
9 / 20 page TC94A39FAG/FB 2003-04-01 9 Pin No. Symbol Pin Name Function and Operation Remarks 8 MVDD 9 MVSS Power supply pins for controller block Power supply pins for the controller block. Normally, VDD = 3.0 to 3.6 V. When only the CPU operates (when the 75-kHz/32.768-kHz oscillator is used), it can operate at VDD = 1.8 to 3.6 V. In the backup state (when the CKSTP instruction is executed), current dissipation decreases (10 mA or below), allowing the power supply voltage to be reduced to 1.0 V. Raising the voltage on MVDD pin from 0 V to 1.8 V or higher triggers a system reset, causing the program to start from address 0 (power-on reset). (Note) At power-on reset operation, allow 1 ms to 50 ms while the device power supply voltage rises. (Note) The backup current is the total of currents for CVDD, MVDD and DVDD. 17 PDO Output pin for a phase error signal between the EFM and PLCK signals. Drives one of four values: AVDD, Hi-Z, VREF, AVSS 18 TMAX TMAX detection result output pin. Longer than specified cycle: Drives a high level (AVDD) Shorter than specified cycle: Drives a low level (AVSS) Within specified cycle: Hi-Z 19 LPFN Inverted input pin for PLL low-pass filter amplifier. 20 LPFO Output pin for PLL low-pass filter amplifier. 21 VCOF VCO filter pin 22 AVSS CD processor control input/output pin Ground pin for analog block ¾ MVDD MVSS AVDD AVSS VCO VREF AVDD LPFN LPFO VREF VCOF AVDD VREF Rout4 AVSS |
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