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TMP86FP24 Fiches technique(PDF) 4 Page - Toshiba Semiconductor |
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TMP86FP24 Fiches technique(HTML) 4 Page - Toshiba Semiconductor |
4 / 217 page TMP86FP24 2007-08-24 86FP24-2 ♦ Serial interface • UART/SIO: 1ch • SIO: 1ch ♦ ROM corrective function • Four register bank • 1 byte or 2 bytes replace mode • Address replace mode ♦ 10-bit successive approximation type AD converter • Analog input: 8 ch ♦ Five key-on wakeup pins ♦ LCD driver/controller • Built-in voltage booster for LCD driver • With display memory (12 bytes) • LCD direct drive capability (Max 24 seg × 4 com) • 1/4, 1/3, 1/2 duties or static drive are programmably selectable ♦ Dual clock operation • Single/dual clock mode ♦ Nine power saving operating modes • STOP mode: Oscillation stops. Battery/capacitor backup. Port output hold/high impedance. • SLOW1, 2 mode: Low power consumption operation using low-frequency clock (32.768 kHz). • IDLE0 mode: CPU stops, and peripherals operate using high-frequency clock of time-base-timer. Release by falling edge of TBTCR <TBTCK> setting. • IDLE1 mode: CPU stops, and peripherals operate using high-frequency clock. Release by interrupts. • IDLE2 mode: CPU stops, and peripherals operate using high and low frequency clock. Release by interrupts. • SLEEP0 mode: CPU stops, and peripherals operate using low-frequency clock of time-base-timer. Release by falling edge of TBTCR <TBTCK> setting. • SLEEP1 mode: CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. • SLEEP2 mode: CPU stops, and peripherals operate using high and low frequency clock. Release by interrupts. ♦ Wide operating voltage: 1.8 to 3.6V at 8 MHz/32.768 kHz 2.7 to 3.6V at 16 MHz/32.768 kHz |
Numéro de pièce similaire - TMP86FP24 |
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Description similaire - TMP86FP24 |
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