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74AUP1G00GW Fiches technique(PDF) 8 Page - NXP Semiconductors |
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74AUP1G00GW Fiches technique(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 8 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate [1] All typical values are measured at nominal VCC. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. Tamb = 25 °C CPD power dissipation capacitance f = 1 MHz; VI = GND to VCC [2] VCC = 0.8 V - 2.6 - pF VCC = 1.1 V to 1.3 V - 2.8 - pF VCC = 1.4 V to 1.6 V - 2.9 - pF VCC = 1.65 V to 1.95 V - 3.1 - pF VCC = 2.3 V to 2.7 V - 3.6 - pF VCC = 3.0 V to 3.6 V - 4.2 - pF Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter Conditions Min Typ [1] Max Unit Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V 2.1 12.2 2.1 13.5 ns VCC = 1.4 V to 1.6 V 1.8 7.8 1.8 8.6 ns VCC = 1.65 V to 1.95 V 1.4 6.2 1.4 6.9 ns VCC = 2.3 V to 2.7 V 1.1 4.7 1.1 5.2 ns VCC = 3.0 V to 3.6 V 1.0 4.2 1.0 4.7 ns CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V 2.2 14.4 2.2 15.9 ns VCC = 1.4 V to 1.6 V 2.2 9.2 2.2 10.2 ns VCC = 1.65 V to 1.95 V 1.9 7.3 1.9 8.1 ns VCC = 2.3 V to 2.7 V 1.3 5.6 1.3 6.2 ns VCC = 3.0 V to 3.6 V 1.2 4.9 1.2 5.4 ns |
Numéro de pièce similaire - 74AUP1G00GW |
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Description similaire - 74AUP1G00GW |
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