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74LV86N Fiches technique(PDF) 7 Page - NXP Semiconductors

No de pièce 74LV86N
Description  Quad 2-input exclusive-OR gate
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LV86N Fiches technique(HTML) 7 Page - NXP Semiconductors

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74LV86_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 27 November 2007
7 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
The input (nA, nB) to output (nY) propagation delays
mna224
nA, nB input
nY output
tPLH
tPHL
GND
VI
VM
VM
VOH
VOL
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
0.5VCC
2.7 V to 3.6 V
1.5 V
1.5 V
≥ 4.5 V
0.5VCC
0.5VCC
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 7.
Load circuit for switching times
VCC
VI
VO
001aaa663
D.U.T.
CL
50 pF
RT
RL
1 k
PULSE
GENERATOR
Table 9.
Test data
Supply voltage
VCC
Input
VI
tr, tf
< 2.7 V
VCC
≤ 2.5 ns
2.7 V to 3.6 V
2.7 V
≤ 2.5 ns
≥ 4.5 V
VCC
≤ 2.5 ns


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