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74HCT240N Fiches technique(PDF) 3 Page - NXP Semiconductors |
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74HCT240N Fiches technique(HTML) 3 Page - NXP Semiconductors |
3 / 18 page 74HC_HCT240_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 2 August 2007 3 of 18 NXP Semiconductors 74HC240; 74HCT240 Octal buffer/line driver; 3-state; inverting 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input Fig 4. Pin configuration DIP20, SO20, (T)SSOP20 Fig 5. Pin configuration DHVQFN20 74HC240 74HCT240 1OE VCC 1A0 2OE 2Y0 1Y0 1A1 2A0 2Y1 1Y1 1A2 2A1 2Y2 1Y2 1A3 2A2 2Y3 1Y3 GND 2A3 001aag233 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aag234 74HC240 74HCT240 Transparent top view 1Y3 1A3 2Y3 GND(1) 2A2 2Y2 1Y2 1A2 2A1 2Y1 1Y1 1A1 2A0 2Y0 1Y0 1A0 2OE 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description 1OE 1 output enable input (active LOW) 1A0 2 data input 2Y0 3 bus output 1A1 4 data input 2Y1 5 bus output 1A2 6 data input 2Y2 7 bus output 1A3 8 data input 2Y3 9 bus output GND 10 ground (0 V) 2A3 11 data input 1Y3 12 bus output 2A2 13 data input 1Y2 14 bus output 2A1 15 data input 1Y1 16 bus output |
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Description similaire - 74HCT240N |
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