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74HC240N Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74HC240N Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 18 page 74HC_HCT240_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 2 August 2007 10 of 18 NXP Semiconductors 74HC240; 74HCT240 Octal buffer/line driver; 3-state; inverting Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Load circuitry for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open PULSE GENERATOR Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC240 VCC 6 ns 15 pF, 50 pF 1 k Ω open GND VCC 74HCT240 3 V 6 ns 15 pF, 50 pF 1 k Ω open GND VCC |
Numéro de pièce similaire - 74HC240N |
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Description similaire - 74HC240N |
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