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CD54HC03 Fiches technique(PDF) 5 Page - Texas Instruments

No de pièce CD54HC03
Description  High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

CD54HC03 Fiches technique(HTML) 5 Page - Texas Instruments

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5
Power Dissipation Capacitance
(Notes 5, 6)
CPD
-
5
-
9
-
----
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = CPD VCC
2 f
i + Σ (CL VCC
2 f
o) + Σ (VL
2/R
L) (Duty Factor “Low”)
where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage, Duty Factor “Low” = percent of
time output is “low”, VL = output voltage, RL = pull-up resistor.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY
TIMES, AND TEST CIRCUIT
FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
INPUT LEVEL
VS
tPZL
VOH
OUTPUT
1k
VCC
50pF
VOL
90%
10%
tTHL
OUTPUT
OPEN
DRAIN
NAND
GATE
VCC
nB(nA)
OUTPUT
nY
tPLZ
nA(nB)
VS
LOW
OFF
LOW
RL
VL
VO
VCC = 5V
±10%
HC/HCT03
VL
RL
RON
VO
0.8V (HCT VIL MAX)
≤ 1.35V (HC VIL MAX)
RON MAX =
65
Ω AT 25oC
4mA
=
0.26V
800
700
600
500
400
300
200
100
0123456789
10
VL, LOAD VOLTAGE (V)
HC
HCT
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
tPHL
tPLH
tTHL
tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
tf = 6ns
90%
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03


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