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TMP470R1B768PGE Fiches technique(PDF) 5 Page - Texas Instruments |
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TMP470R1B768PGE Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 50 page www.ti.com Device Characteristics TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108A – AUGUST 2005 – REVISED AUGUST 2006 Table 1 identifies all the characteristics of the TMS470R1B768 device except the SYSTEM and CPU, which are generic. Table 1. Device Characteristics DEVICE DESCRIPTION CHARACTERISTICS COMMENTS For B768 TMS470R1B768 MEMORY For the number of memory selects on this device, see Table 3, Memory Selection Assignment. INTERNAL MEMORY Pipeline/Non-Pipeline Flash is pipeline-capable. The B768 RAM is implemented in one 48K array selected by two 768K-Byte flash memory-select signals (see Table 3, Memory Selection 48K-Byte SRAM Assignment). PERIPHERALS For the device-specific interrupt priority configurations, see Table 7, Interrupt Priority (IEM and CIM). And for the 1K peripheral address ranges and their peripheral selects, see Table 5, B768 Peripherals, System Module, and Flash Base Addresses. CLOCK ZPLL Zero-pin PLL has no external loop filter pins. GENERAL-PURPOSE I/Os 15 I/O Port A has eight (8) external pins, port B has one (1), port C has 1 Input only three (3), and port D has four (4). ECP YES SCI 2 (3-pin) SCI1 and SCI2 CAN (HECC and/or SCC) 3 HECCs Three HECCs (HECC1, HECC2, and HECC3) SPI (5-pin, 4-pin or 3-pin) 5 (5-pin) SPI1, SPI2, SPI3, SPI4, and SPI5 The B768 device has both the logic and registers for a full 32-I/O HET implemented and all 32 pins are available externally. The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is HET with XOR Share 32 I/O independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Refe4rence Guide (literature number SPNU199). HET RAM 128-Instruction Capacity The B768 device has both the logic and registers for a full 10-bit, 16-channel MibADC 16-channel MibADC implemented and all 16 pins are available 256-word FIFO externally. CORE VOLTAGE 1.81–2.05 V I/O VOLTAGE 3.0–3.6 V PINS 144 PACKAGE PGE 5 Submit Documentation Feedback |
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