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TPIC2802 Fiches technique(PDF) 5 Page - Texas Instruments |
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TPIC2802 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 13 page TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 2–5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating virtual junction temperature range (unless otherwise noted) (continued) driver array outputs (Y0 to Y7) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOK Output clamp voltage IO = 0.5 A, Output programmed off and current shunted to ground 45 49 V IOL = 0.175 A 1 V With one output IOL = 0.5 A 1 1.3 V VO(on) On-state output voltage programmed on and dti IOL = 0.75 A 1.2 1.5 V () conducting IOL = 1 A, During unlatch disable 1.4 1.6 V VTOS Out-of-saturation threshold voltage With output programmed on and an overcurrent fault condition 1.6 1.8 2.1 V IO(off) Off-state output current VO = 24 V with output programmed off 600 µA IO(cl) Output current limit VO = 3 V with output programmed on 1 1.8 A Internal output pulldown resistor 40 90 k Ω shift register (Inputs SI, SCLK, SCLK, and RST) PARAMETER TEST CONDITIONS MIN MAX UNIT VIT+ Positive-going threshold voltage 0.75 VCC V VIT – Negative-going threshold voltage 0.1 VCC V Vhys Hysteresis voltage (VIT+ – VIT–) 0.85 2.5 V II Input current VI = 0 to VCC ±10 µA Ci Input capacitance VI = 0 to VCC 20 pF shift register (output SO) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOL Low-level output voltage IO = 1.6 mA 0.2 0.4 V VOH High-level output voltage IO = – 0.8 mA VCC –1.3 V IO Output current VO = 0 to VCC, SIOE input high ±20 µA Co Output capacitance VO = 0 to VCC, SIOE input high 20 pF † All typical values are at VCC = 5 V, TJ = 25°C. timing requirements over recommended ranges of supply voltage and operating case temperature (see Figure 1) MIN MAX UNIT fclock Clock frequency, SCLK 0 1 MHz tw(SCLKH) Pulse duration, SCLK high See Note 7 410 ns tw(SCLKL) Pulse duration, SCLK low 410 ns tw(RST) Pulse duration, RST low 1200 ns tsu1 Setup time, SIOE ↓ before SCLK↑ 1 µs tsu2 Setup time, SCLK ↓ before SIOE↑ 1 µs tsu3 Setup time, SI high before SCLK ↓ 150 ns th1 Hold time, SI low after SCLK ↓ 150 ns tr Rise time, SCLK, SI, SIOE 90 ns tf Fall time, SCLK, SI, SIOE 90 ns NOTE 7: For cascaded operation, the clock pulse durations (tw(SCLKL) and tw(SCLKH)) must be a minimum of 700 ns (giving a maximum clock frequency of 632 kHz). |
Numéro de pièce similaire - TPIC2802 |
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Description similaire - TPIC2802 |
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