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CAT5419 Fiches technique(PDF) 5 Page - Catalyst Semiconductor

No de pièce CAT5419
Description  Dual Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface
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Fabricant  CATALYST [Catalyst Semiconductor]
Site Internet  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT5419 Fiches technique(HTML) 5 Page - Catalyst Semiconductor

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CAT5419
© Catalyst Semiconductor, Inc.
5
Doc. No. MD-2115 Rev. H
Characteristics subject to change without notice
WRITE CYCLES LIMITS
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
NEND
(1)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR
(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP
(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH
(1)(2)
Latch-Up
JEDEC Standard 17
100
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Bus Timing
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL


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