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CAT5269 Fiches technique(PDF) 4 Page - Catalyst Semiconductor

No de pièce CAT5269
Description  Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and 2-wire Interface
Download  16 Pages
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Fabricant  CATALYST [Catalyst Semiconductor]
Site Internet  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT5269 Fiches technique(HTML) 4 Page - Catalyst Semiconductor

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CAT5269
Doc. No. MD-2123 Rev. C
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC1
Power Supply Current
fSCL = 400kHz, SDA = Open
VCC = 6V, Inputs = GND
1
mA
ICC2
Power Supply Current
Non-volatile WRITE
fSCK = 400kHz, SDA Open
VCC = 6V, Input = GND
5
mA
ISB
Standby Current (VCC = 5.0V)
VIN = GND or VCC, SDA = Open
5
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0V) IOL = 3mA
0.4
V
VOL2
Output Low Voltage (VCC = 1.8V) IOL = 1.5mA
0.5
V
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
Test
Conditions
Max
Units
CI/O
(1)
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
(1)
Input Capacitance (A0, A1, A2, A3, SCL, WP
¯¯¯)
VIN = 0V
6
pF
A.C. CHARACTERISTICS
2.5V - 6.0V
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
TI
(1)
Noise Suppression Time Constant at SCL, SDA Inputs
200
ns
tAA
SLC Low to SDA Data Out and ACK Out
1
µs
tBUF
(1)
Time the bus must be free before a new transmission can start
1.2
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tLOW
Clock Low Period
1.2
µs
tHIGH
Clock High Period
0.6
µs
tSU:STA
Start Condition SetupTime (for a Repeated Start Condition)
0.6
µs
tHD:DAT
Data in Hold Time
0
ns
tSU:DAT
Data in Setup Time
50
ns
tR
(1)
SDA and SCL Rise Time
0.3
µs
tF
(1)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
0.6
µs
tDH
Data Out Hold Time
100
ns
Note:
This parameter is tested initially and after a design or process change that affects the parameter.


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