SN54ABT8245, SN74ABT8245

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

14

POST OFFICE BOX 655303

pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge

of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge

of TCK. This data also is updated in the shadow latches of the selected input BSCs and, thereby, applied to the

inputs of the normal on-chip logic. Figures 4 and 5 illustrate the 16-bit linear-feedback shift-register algorithms

through which the patterns are generated. An initial seed value should be scanned into the BSR before

performing this operation. Note that a seed value of all zeroes does not produce additional patterns.

=

A8-I

B8-O

A7-I

A6-I

A5-I

A4-I

A3-I

A2-I

A1-I

B7-O

B6-O

B5-O

B4-O

B3-O

B2-O

B1-O

Figure 4. 16-Bit PRPG Configuration (OEA = 0, OEB = 1)

=

B8-I

A8-O

B7-I

B6-I

B5-I

B4-I

B3-I

B2-I

B1-I

A7-O

A6-O

A5-O

A4-O

A3-O

A2-O

A1-O

Figure 5. 16-Bit PRPG Configuration (OEA = 1, OEB = 0)