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ST72324BJ Fiches technique(PDF) 39 Page - STMicroelectronics

No de pièce ST72324BJ
Description  8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
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Site Internet  http://www.st.com
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ST72324BJ Fiches technique(HTML) 39 Page - STMicroelectronics

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ST72324B
Interrupts
39/188
peripheral control register. The general sequence for clearing an interrupt is based on an
access to the status register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) is therefore lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column Exit from HALT in Table 24: Interrupt mapping). When several pending interrupts are
present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from
Halt mode capability and it is selected through the same decision process shown in
Figure 19.
Note:
If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
Figure 20 and Figure 21 show two different interrupt management modes. The first is called
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in Figure 21. The interrupt hardware priority is given in order from the lowest to the highest
as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.
Warning:
A stack overflow may occur without notifying the software of
the failure.
Figure 20.
Concurrent interrupt management
Main
IT4
IT2
IT1
TRAP
IT1
Main
IT0
I1
Software
3
3
3
3
3
3/0
3
11
11
11
11
11
11/10
11
RIM
IT3
I0
10
priority
level


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