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ADCMP609BRMZ-REEL71 Fiches technique(PDF) 8 Page - Analog Devices |
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ADCMP609BRMZ-REEL71 Fiches technique(HTML) 8 Page - Analog Devices |
8 / 12 page ADCMP609 Rev. 0 | Page 8 of 12 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP609 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCC) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 0.1 μF bypass capacitor should be placed as close as possible to each VCC supply pin. The capacitor should be con- nected to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. TTL-/CMOS-COMPATIBLE OUTPUT STAGE Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The outputs of the ADCMP609 are designed to directly drive one Schottky TTL or three low power Schottky TTL loads (or an equivalent). For large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. With the rated 15 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time. Because of this, the total propagation delay decreases as VCC decreases, and instability in the power supply may appear as excess delay dispersion. Delay is measured to the 50% point for whatever supply is in use; thus, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (Figure 11). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. OUTPUT Q2 Q1 +IN –IN OUTPUT STAGE VLOGIC GAIN STAGE A2 A1 AV Figure 11. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage OPTIMIZING PERFORMANCE As with any high speed comparator, proper design and layout tech- niques are essential for obtaining the specified performance. Stray capacitance, inductance, common power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Higher impedances encourage undesired coupling. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP609 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mV to VCC – 1 V. Propagation delay dispersion is the variation in propa- gation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). |
Numéro de pièce similaire - ADCMP609BRMZ-REEL71 |
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Description similaire - ADCMP609BRMZ-REEL71 |
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