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SI5367C-B-GQ Fiches technique(PDF) 10 Page - Silicon Laboratories |
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SI5367C-B-GQ Fiches technique(HTML) 10 Page - Silicon Laboratories |
10 / 18 page Si5367 10 Preliminary Rev. 0.3 39 40 CKIN3+ CKIN3– IMULTI Clock Input 3. Differential clock input. This input can also be driven with a single-ended signal. CKIN3 serves as the frame sync input associated with the CKIN1 clock when CK_CONFIG_REG =1. 44 45 CKIN1+ CKIN1– IMULTI Clock Input 1. Differential clock input. This input can also be driven with a single-ended signal. 58 C1A O LVCMOS CKIN1 Active Clock Indicator. This pin serves as the CKIN1 active clock indicator. The CK1_ACTV_REG bit always reflects the active clock sta- tus for CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected on the C1A pin with active polarity con- trolled by the CK_ACTV_POL bit. If CK1_ACTV_PIN = 0, this output tristates. 59 C2A O LVCMOS CKIN2 Active Clock Indicator. This pin serves as the CKIN2 active clock indicator. The CK2_ACTV_REG bit always reflects the active clock sta- tus for CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected on the C2A pin with active polarity con- trolled by the CK_ACTV_POL bit. If CK2_ACTV_PIN = 0, this output tristates. 60 SCL I LVCMOS Serial Clock. This pin functions as the serial port clock input for both SPI and I2C modes. This pin has a weak pull-down. 61 SDA_SDO I/O LVCMOS Serial Data. In I2C microprocessor control mode (CMODE = 0), this pin functions as the bidirectional serial data port.In SPI microprocessor control mode (CMODE = 1), this pin functions as the serial data output. 68 69 A0 A1 ILVCMOS Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. In SPI control mode (CMODE = 1), these pins are ignored. This pin has a weak pull-down. 70 A2_SS ILVCMOS Serial Port Address/Slave Select. In I2C microprocessor control mode (CMODE = 0), this pin functions as a hardware controlled address bit. In SPI microprocessor control mode (CMODE = 1), this pin functions as the slave select input. This pin has a weak pull-down. Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. |
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