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SI5018-BM Fiches technique(PDF) 1 Page - Silicon Laboratories |
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SI5018-BM Fiches technique(HTML) 1 Page - Silicon Laboratories |
1 / 22 page Rev. 1.2 1/04 Copyright © 2004 by Silicon Laboratories Si5018-DS12 Si5018 SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC Features Complete high-speed, low-power, CDR solution includes the following: Applications description The Si5018 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/STM-16 data rates. In addition, support for 2.7 Gbps data streams is also provided for applications that employ forward error correction (FEC). DSPLL™ technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5018 represents a new standard in low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C). Functional Block Diagram ! Supports OC-48 /STM-16 & FEC ! Low power—270 mW (typ OC-48) ! Small footprint: 4x4 mm ! DSPLL™ Eliminates external loop filter components ! 3.3 V tolerant control inputs ! Exceeds all SONET/SDH jitter specifications ! Jitter generation 3.0 mUIrms (typ) ! Device powerdown ! Loss-of-lock indicator ! Single 2.5 V Supply ! SONET/SDH/ATM routers ! Add/drop multiplexers ! Digital cross connects ! SONET/SDH test equipment ! Optical transceiver modules ! SONET/SDH regenerators ! Board level serial links DSPLLTM Pha s e-Locke d Loop Retim er BU F BU F BU F DIN + DIN – REXT LO L 2 REF C LKIN + REF C LKIN – 2 DOUT + DOUT – CLKOUT + CLKOUT – PW RDN/C AL 2 2 Bias Ordering Information: See page 17. Pin Assignments Si5018 GND Pad Connection 15 14 13 12 11 PWRDN/CAL DOUT+ VDD DOUT– VDD 1 2 3 4 5 VDD GND REFCLK– REXT REFCLK+ 20 19 18 17 16 6 7 8 9 10 |
Numéro de pièce similaire - SI5018-BM |
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