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STAC9271 Fiches technique(PDF) 20 Page - Integrated Device Technology

No de pièce STAC9271
Description  10-CHANNEL HIGH DEFINITION AUDIO CODEC
Download  223 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

STAC9271 Fiches technique(HTML) 20 Page - Integrated Device Technology

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STAC9271/9272/9273/9274
10-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
IDT™
10-CHANNEL HIGH DEFINITION AUDIO CODEC
20
STAC9271/9272/9273/9274 V 1.0 MARCH2007
IDT CONFIDENTIAL
1. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth.
2. ± 3dB limits for Line Output and 0dB gain, at -20dBV
3. Amplitude of THD+N, measured with A-weighting filter, over 20 Hz to 20 KHz bandwidth.
4. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz
bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio.)
5. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency.
6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a
bandwidth 28.8 KHz to 100 KHz, with respect to a 1 Vrms DAC output.
8. Can be set to 0.5 or 0.8 AVdd.
40dB Mic Boost Enabled THD+N
5 mV Input
All
55
dB
Power Supply
Power Supply Rejection Ratio
1 KHz
All
-
-70
-
dB
Power Supply Rejection Ratio
20 KHz
All
-
-40
-
dB
D0 Didd
3.3 V
75
90
mA
D0 Aidd
5.0 V, 4.5 V, & 4.0 V, 3.3 V
85
mA
D1 Didd
3.3 V
75
90
mA
D1 Aidd
5.0 V, 4.5 V, & 4.0 V, 3.3 V
85
mA
D2 Didd
3.3 V
23
30
mA
D2 Aidd
5.0 V, 4.5 V, & 4.0 V, 3.3 V
58
mA
D3 Didd
3.3 V
23
30
mA
D3 Aidd
5.0 V, 4.5 V, & 4.0 V, 3.3 V
37
mA
One Stereo ADC Didd
3.3 V
8
10
mA
One Stereo ADC Aidd
5.0 V, 4.5 V, & 4.0 V, 3.3 V
10
mA
One Stereo DAC Didd
3.3 V
3
5
mA
One Stereo DAC Aidd
5.0 V, 4.5 V, & 4.0 V, 3.3 V
2
mA
CD Input
CD Common Mode Rejection (CMR)
All
50
55
dB
Voltage Reference Outputs
VREFout (Note 8)
All
-
0.5 X
AVdd
-V
VREFILT (VAG)
All
0.45X
AVdd
V
Phased Locked Loop
PLL lock time
All
96
200
µsec
PLL (or Azalia Bit CLK) 24 MHz clock jitter
All
150
500
psec
Parameter
Conditions
AVdd
Min
Typ
Max
Unit


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