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UDA1341TS Fiches technique(PDF) 25 Page - NXP Semiconductors |
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UDA1341TS Fiches technique(HTML) 25 Page - NXP Semiconductors |
25 / 32 page 1998 Dec 18 25 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 12 AC CHARACTERISTICS (DIGITAL) VDDD =VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing (see Fig.8) Tsys clock cycle time fsys = 256fs 78 88 131 ns fsys = 384fs 52 59 87 ns fsys = 512fs 39 44 66 ns tCWL LOW-level pulse width fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns tCWH HIGH-level pulse width fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns Serial input/output data timing (see Fig.9) Tcy bit clock cycle time 300 −− ns tBCK(H) bit clock HIGH time 100 −− ns tBCK(L) bit clock LOW time 100 −− ns tr rise time −− 20 ns tf fall time −− 20 ns ts;DATI data input set-up time 20 −− ns th;DATI data input hold time 0 −− ns td;DATO(BCK) data output delay time (from BCK falling edge) −− 80 ns td;DATO(WS) data output delay time (from WS edge) MSB-justified format −− 80 ns th;DATO data output hold time 0 −− ns ts;WS word select set-up time 20 −− ns th;WS word select hold time 10 −− ns Microcontroller L3-interface timing (see Figs 5 and 6) Tcy(CLK)(L3) L3CLOCK 500 −− ns tCLK(L3)H L3CLOCK HIGH time 250 −− ns tCLK(L3)L L3CLOCK LOW time 250 −− ns tsu(L3)A L3MODE set-up time addressing mode 190 −− ns th(L3)A L3MODE hold time addressing mode 190 −− ns tsu(L3)D L3MODE set-up time data transfer mode 190 −− ns th(L3)D L3MODE hold time data transfer mode 190 −− ns tsu(L3)DA L3DATA set-up time data transfer and addressing mode 190 −− ns th(L3)DA L3DATA hold time data transfer and addressing mode 30 −− ns tstp(L3) L3MODE halt time 190 −− ns |
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