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74AUP1G04 Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74AUP1G04 Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 16 page 74AUP1G04_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 28 June 2006 2 of 16 Philips Semiconductors 74AUP1G04 Low-power inverter 3. Ordering information 4. Marking 5. Functional diagram 6. Pinning information 6.1 Pinning Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G04GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G04GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AUP1G04GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 Table 2. Marking Type number Marking code 74AUP1G04GW pC 74AUP1G04GM pC 74AUP1G04GF pC Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram mna108 AY 2 4 mna109 4 1 2 mna110 A Y Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP1G04 n.c. VCC A GND Y 001aaf022 1 2 3 5 4 74AUP1G04 A 001aaf023 n.c. GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 74AUP1G04 A 001aaf024 n.c. GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 |
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