Moteur de recherche de fiches techniques de composants électroniques
  French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

AD5025BRUZ Fiches technique(PDF) 24 Page - Analog Devices

No de pièce AD5025BRUZ
Description  Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
Download  33 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5025BRUZ Fiches technique(HTML) 24 Page - Analog Devices

Back Button AD5025BRUZ Datasheet HTML 20Page - Analog Devices AD5025BRUZ Datasheet HTML 21Page - Analog Devices AD5025BRUZ Datasheet HTML 22Page - Analog Devices AD5025BRUZ Datasheet HTML 23Page - Analog Devices AD5025BRUZ Datasheet HTML 24Page - Analog Devices AD5025BRUZ Datasheet HTML 25Page - Analog Devices AD5025BRUZ Datasheet HTML 26Page - Analog Devices AD5025BRUZ Datasheet HTML 27Page - Analog Devices AD5025BRUZ Datasheet HTML 28Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 33 page
background image
AD5025/45/65
Preliminary Technical Data
INPUT SHIFT REGISTER
The AD5025/45/65 input shift register is 32 bits wide (see
Figure 43). The first four bits are don’t cares. The next four bits
are the command bits, C3 to C0 (see Table 8), followed by the 4­
bit DAC address bits, A3 to A0 (see Table 9) and finally the bit
data-word. The data-word comprises either 12-/14 or 16-bit
input code followed by 8-/6 or 4 don’t care bits for the
AD5025/45/65 (see Figure 43). These data bits are transferred to
the DAC register on the 32nd falling edge of SCLK.
DB31 (MSB)
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 46).
DB0 (LSB)
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DATA BITS
C3
C2
C1
C0
A3
A2
A1
A0
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
COMMAND BITS
ADDRESS BITS
Figure 43. AD5065 Input Register Content
DB31 (MSB)
DB0 (LSB)
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 44. AD5045 Input Register Content
DB31 (MSB)
DB0 (LSB)
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 45. AD5025 Input Register Content
SCLK
DB31
DB0
DB31
DB0
SYNC
DIN
INVALID WRITE SEQUENCE:
VALID WRITE SEQUENCE, OUTPUT UPDATES
SYNC HIGH BEFORE 32ND FALLING EDGE
ON THE 32ND FALLING EDGE
Figure 46. SYNC Interrupt Facility
Rev. PrB | Page 24 of 3
3


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33 


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn