Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

AD5025 Datasheet(Fiches technique) 6 Page - Analog Devices

Numéro de pièce AD5025
Description  Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
Télécharger  33 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5025 Datasheet(HTML) 6 Page - Analog Devices

Back Button AD5025 Datenblatt HTML 2Page - Analog Devices AD5025 Datenblatt HTML 3Page - Analog Devices AD5025 Datenblatt HTML 4Page - Analog Devices AD5025 Datenblatt HTML 5Page - Analog Devices AD5025 Datasheet HTML 6Page - Analog Devices AD5025 Datenblatt HTML 7Page - Analog Devices AD5025 Datenblatt HTML 8Page - Analog Devices AD5025 Datenblatt HTML 9Page - Analog Devices AD5025 Datenblatt HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 33 page
background image
AD5025/45/65
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 5. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
t11
t2
t3
t4
t5
t6
t7
t8
t8
t9
t10
t11
t12
t13
t14
t15
t162, 3
t173
t183
t193
t20
20
10
10
16.5
5
5
0
1.9
10.5
16.5
0
20
20
10
10
10.6
22
5
8
0
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
us min
us min
ns min
ns min
ns min
ns min
ns min
ns min
us min
ns max
ns min
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
PDL pulse width activation time
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2 Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode.
3 Daisy-chain mode only.
2mA
IOL
2mA
IOH
VOH (MIN)
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. PrB | Page 6 of 3
3


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33 


Datasheet Download

Go To PDF Page


Lien URL



Privacy Policy
ALLDATASHEET.FR
AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicit   |   Contactez-nous   |   Politique de confidentialit   |   Echange de liens   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn