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TDA8705AT Fiches technique(PDF) 7 Page - NXP Semiconductors |
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TDA8705AT Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 1996 Jan 12 7 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A Switching characteristics CLOCK INPUT CLK; note 1; see Fig.3 fclk(max) maximum clock frequency 80 −− MHz tCPH clock pulse width HIGH 5.5 −− ns tCPL clock pulse width LOW 5.5 −− ns Analog signal processing LINEARITY ILE DC integral linearity error −±0.25 ±0.5 LSB DLE DC differential linearity error −±0.25 ±0.5 LSB AILE AC integral linearity error note 3 −±0.5 ±1.0 LSB OFE offset error between A and B fi = 10 MHz; fclk = 40 MHz; note 4 ±1 −±2 LSB GE gain error between A and B fi = 10 MHz; fclk = 40 MHz; note 4 ±1 −±2 LSB MID middle scale output code (A and B) 31 − 32 BANDWIDTH;fclk =80MHz B −0.5 dB analog bandwidth full-scale sine wave; note 5 − 50 − MHz tSTLH analog input settling time LOW-to-HIGH full-scale square wave; Fig.4; note 6 − 8 − ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave; Fig.4; note 6 − 5 − ns HARMONICS;fclk =40MHZ; see Fig.5 h1 fundamental harmonics (full scale) fi = 20 MHz −− 0dB hall harmonics (full scale); all components fi = 20 MHz second harmonics −−45 − dB third harmonics −−41 − dB THD total harmonic distortion fi = 20 MHz −−39 −34 dB SIGNAL-TO-NOISE RATIO; note 7; see Fig.5 S/N signal-to-noise ratio (full scale) without harmonics; fclk = 80 MHz; fi = 20 MHz 33 36 − dB EFFECTIVE BITS; note 7; see Fig.5 EB effective bits fclk = 80 MHz fi = 10 MHz − 5.7 − bits fi = 20 MHz − 5.5 − bits fi = 30 MHz − 5.1 − bits SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
Numéro de pièce similaire - TDA8705AT |
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Description similaire - TDA8705AT |
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