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TDA8007BHL Fiches technique(PDF) 7 Page - NXP Semiconductors |
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TDA8007BHL Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 36 page 2000 Nov 09 7 Philips Semiconductors Product specification Double multiprotocol IC card interface TDA8007B FUNCTIONAL DESCRIPTION Throughout this specification, it is assumed that the reader is aware of ISO 7816 norm terminology. Interface control The TDA8007B can be controlled via an 8-bit parallel bus (bits D0 to D7). If a microcontroller with a multiplexed address/data bus (such as the 80C51) is used, then D0 to D7 may be directly connected to P0 to P7. When CS is LOW, the demultiplexing of address and data is performed internally using the ALE signal, a LOW pulse on pin RD allows the selected register to be read, a LOW pulse on pin WR allows the selected register to be written to. The TDA8007B automatically switches to the multiplexed bus configuration if a rising edge is detected on pin ALE. In this event, AD0 to AD3 play no role and may be tied to VDD or GND. Using a 80C51 microcontroller, the TDA8007B is simply controlled with MOVX instructions. If ALE is tied to VDD or GND, then the TDA8007B will be in the non-multiplexed configuration. In this case, the address bits are external pins AD0 to AD3, RD is the read/write control signal, and WR is a data write or read active LOW enable signal. In both configurations, the TDA8007B is selected only when CS is LOW. INT is an active LOW interrupt signal. In non-multiplexed bus configuration, CS and EN play the same role. In read operations (RD/WR is HIGH), the data corresponding to the chosen address is available on the bus when both CS and EN are LOW. In write operations, the data present on the bus is written when signals RD/WR, CS and EN become LOW. handbook, full pagewidth LATCH MUX MUX addresses FCE679 RD WR REC CS AD0 to AD3 ALE WR RD D0 to D7 REGISTERS Fig.3 Multiplexed bus recognition. |
Numéro de pièce similaire - TDA8007BHL |
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