TDA1546T datasheet(9/40 Pages) PHILIPS

No de pièce	TDA1546T

Description	Bitstream Continuous Calibration DAC with digital sound processing BCC-DAC

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Fabricant	PHILIPS [NXP Semiconductors]

Site Internet	http://www.nxp.com

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January 1995

9

Philips Semiconductors

Preliminary speciﬁcation

Bitstream Continuous Calibration DAC with

digital sound processing (BCC-DAC)

TDA1546T

7

FUNCTIONAL DESCRIPTION

The TDA1546T CMOS digital-to-analog bitstream

converter incorporates an up-sampling digital filter and

noise shaper which increase the oversample rate of 1fs

input data to 128fs in the normal-speed mode. This

high-rate oversampling, together with the 5-bit DAC,

enables the filtering required for waveform smoothing and

out-of-band noise reduction to be achieved by simple

first-order analog post-filtering.

In the double-speed mode, the input sample frequency is

twice that of the normal-speed mode, as is the signal

bandwidth. The TDA1546T is able to distinguish between

the two modes (by means of a special programming bit),

so that in the double-speed mode, only half the amount of

oversampling is applied, and digital filtering is applied over

double the bandwidth compared to normal-speed. Thus in

the double-speed mode, the input sample rate of 1fs input

data is up-sampled by a factor 64fs, achieving the same

absolute output sample frequency as in normal-speed

mode.

In the block diagram, Fig.2, a general subdivision into main

functional Sections is illustrated. The actual signal

processing takes place in the digital signal processing

block. The two blocks named microcontroller interface and

clock generation and distribution fulfil a general auxiliary

function to the audio data processing path. The

microcontroller interface provides access to all the blocks

that require, or allow, configuration or selection and

processes the data readout from the peak detection block,

all via a simple three-line interface. The clock generation

and distribution section, which is driven by the external

system clock or crystal oscillator, provides the data

processing blocks with time bases and controls the system

mode dependent frequency settings. The following

sections give detailed explanations of the operation of

each block and their setting options processed by the

microcontroller interface, the use of the microcontroller

interface and of the operation of the clock section with its

various system settings.

7.1

Clock generation and distribution

The TDA1546T has an internal clock generator that may

be used by connecting a crystal of 11.2896 MHz (256fs) or

16.9344 MHz (384fs) between pins XTAL1 and XTAL2.

This mode is used when the TDA1546T is the master in

the system. The circuit diagram of Fig.4 shows the typical

connection of the external oscillator circuitry for master

mode operation.

Alternatively, the TDA1546T can also operate in slave

mode. Figure 5 shows how to connect for slave mode

operation. In this mode, pin XTAL1 receives an input clock

of 256 or 384fs (fs = 32, 44.1 or 48 kHz) and voltage levels

of 0 V to 5 V by AC coupling and attenuation.

The CDEC output (pin 16) contains a buffered version of

the system clock for external use. The clock selection pin

CKSL is used to select between system clock frequency

ratios. Its effect is shown in Table 1.

Table 1

System clock selection

PIN CKSL

SYSTEM CLOCK

CDEC OUTPUT

0

256fs

1

384fs

Fig.4 External crystal oscillator circuit.

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