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SL1ICS3001 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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SL1ICS3001 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 22 page I•CODE1 Chip Specification Rev. 2.1 May 2000 SL040521.doc/M Public Page 11 of 22 8 Documentation 8.1 Delivery Documentation Each wafer container and each larger shipment container is individually marked with the identification information as follows: • Diffusion Batch number (wafer lot number) • Part designation (type) with revision number • Ordering code (see chapter 4) • Date code of lot acceptation • Good die quantity The print out of the final test results is attached to the packing and contains the good die quantity related to every wafer number. 8.2 Fail-Die Identification Every die is electrically tested according to data sheet. Identification of chips, which do not confirm with the electrical parameters of the data sheet is done by inking and/or wafer mapping (all dies at wafer periphery are identified by ‘FAIL’). 8.2.1 Ink Dot Specification Diameter: min. 0.4 mm Height: max. 20 µm Colour: black Position: central third of die (x, y direction) Attributes: opaque, water resistant NOTE: Uncompleted dies with an area < 95 % (wafer periphery) are not inked! 8.2.2 Wafer Mapping Wafer mapping for failed die identification is available on Floppy-Disk. Format: Electroglas ESC–ASCEND on 3.5 ″ Floppy-Disk NOTE: The wafer map refers to unsawn wafers. At sawn wafers (on FFC) additional ICs might be inked (marked as fail) if damaged during the sawing process (compared to wafer map)! See Appendix D for an example of the wafer map. |
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