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ST16C554CQ64 Fiches technique(PDF) 4 Page - Exar Corporation

No de pièce ST16C554CQ64
Description  2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
Download  39 Pages
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Fabricant  EXAR [Exar Corporation]
Site Internet  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C554CQ64 Fiches technique(HTML) 4 Page - Exar Corporation

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ST16C554/554D
4
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
REV. 4.0.1
INTA
(IRQ#)
6
15
O
(OD)
When 16/68# pin is HIGH for Intel bus interface, this ouput becomes channel A
interrupt output. The output state is defined by the user and through the soft-
ware setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a
logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0
(default). See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output becomes device
interrupt output (active low, open drain). An external pull-up resistor is required
for proper operation.
INTB
INTC
INTD
(N.C.)
12
37
43
21
49
55
O
When 16/68# pin is HIGH for Intel bus interface, these ouputs become the inter-
rupt outputs for channels B, C, and D. The output state is defined by the user
through the software setting of MCR[3]. The interrupt outputs are set to the
active mode when MCR[3] is set to a logic 1 and are set to the three state mode
when MCR[3] is set to a logic 0 (default). See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, these outputs are unused
and will stay at logic zero level. Leave these outputs unconnected.
INTSEL
-
65
I
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is HIGH for Intel bus interface, this pin can be used in conjunc-
tion with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3
and enable the interrupt outputs. Interrupt outputs are enabled continuously
when this pin is HIGH. MCR bit-3 enables and disables the interrupt output
pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output.
See MCR bit-3 description for full detail. This pin must be LOW in the Motorola
bus interface mode. For the 64 pin packages, this pin is bonded to VCC inter-
nally in the ST16C554DCQ64 so the INT outputs operate in the continuous
interrupt mode. This pin is bonded to GND internally in the ST16C554CQ64 and
therefore requires setting MCR bit-3 for enabling the interrupt output pins.
TXRDY#
-
39
O
Transmitter Ready (active low). This output is a logically ANDed status of
TXRDY# A-D. See Table 5. If this output is unused, leave it unconnected.
RXRDY#
-
38
O
Receiver Ready (active low). This output is a logically ANDed status of RXRDY#
A-D. See Table 5. If this output is unused, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
8
10
39
41
17
19
51
53
O
UART channels A-D Transmit Data and infrared transmit data. In this mode, the
TX signal will be HIGH during reset, or idle (no data).
RXA
RXB
RXC
RXD
62
20
29
51
7
29
41
63
I
UART channel A-D Receive Data. Normal receive data input must idle HIGH.
RTSA#
RTSB#
RTSC#
RTSD#
5
13
36
44
14
22
48
56
O
UART channels A-D Request-to-Send (active low) or general purpose output. If
these outputs are not used, leave them unconnected.
CTSA#
CTSB#
CTSC#
CTSD#
2
16
33
47
11
25
45
59
I
UART channels A-D Clear-to-Send (active low) or general purpose input. These
inputs should be connected to VCC when not used.
Pin Description
NAME
64-LQFP
PIN #
68-PLCC
PIN#
TYPE
DESCRIPTION


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