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SN74GTL16923DGGR Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74GTL16923DGGR Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 13 page www.ti.com FEATURES DESCRIPTION/ORDERING INFORMATION DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CEAB 1A1 GND 1A2 1A3 GND VCC 1A4 GND 1A5 1A6 GND 1A7 1A8 GND 1A9 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 VCC GND 2A7 2A8 GND 2A9 CEBA CLKAB 1OEAB 1OEBA 1B1 GND 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 GND 1B9 2B1 GND 2B2 2B3 GND 2B4 2B5 2B6 VREF 2B7 2B8 GND 2B9 2OEBA 2OEAB CLKBA SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED APRIL 2005 • Member of the Texas Instruments Widebus™ Family • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference • D-Type Flip-Flops With Qualified Storage Enable • Translates Between GTL/GTL+ Signal Levels and LVTTL Logic Levels • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltages With 3.3-V VCC) • Ioff Supports Partial-Power-Down Mode Operation • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) The SN74GTL16923 is an 18-bit registered bus transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two 9-bit transceivers with individual output-enable controls and contains D-type flip-flops for temporary storage of data flowing in either direction. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. <br/> The user has the flexibility of using this device at either GTL (V TT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (V TT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels. All inputs can be driven from either 3.3-V or 5-V devices, which allows use in a mixed 3.3-V/5-V system environment. V REF is the reference input voltage for the B port. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1996–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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