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TPS75118QPWPRG4 Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS75118QPWPRG4 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 35 page TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS SLVS241B – MARCH 2000 – REVISED JUNE 2003 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS753xxQ RESET timing diagram NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VI Vres (see Note A) Vres t t t VO Threshold Voltage RESET Output 100 ms Delay 100 ms Delay Output Undefined Output Undefined VIT + (see Note B) Less than 5% of the output voltage B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. VIT + (see Note B) VIT – (see Note B) VIT – (see Note B) |
Numéro de pièce similaire - TPS75118QPWPRG4 |
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Description similaire - TPS75118QPWPRG4 |
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