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TPS79613DRBT Fiches technique(PDF) 2 Page - Texas Instruments

No de pièce TPS79613DRBT
Description  ULTRALOW-NOISE, HIGH PSRR, FAST, RF, 1A LOW-DROPOUT LINEAR REGULATORS
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS79613DRBT Fiches technique(HTML) 2 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
TPS796xx
SLVS351I – SEPTEMBER 2002 – REVISED MAY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
PRODUCT
VOUT(2)
TPS796xxyyyz
XX is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Output voltages from 1.3V to 4.9V in 100mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
over operating temperature range (unless otherwise noted)(1)
UNIT
VIN range
–0.3V to 6V
VEN range
–0.3V to VIN + 0.3V
VOUT range
6V
Peak output current
Internally limited
ESD rating, HBM
2kV
ESD rating, CDM
500V
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
–40
°C to +150°C
Storage temperature range, Tstg
–65
°C to +150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
BOARD
RθJC
RθJA
DDPAK
High-K(1)
2
°C/W
23
°C/W
SOT223
Low-K(2)
15
°C/W
53
°C/W
3
× 3 SON
High-K(1)
1.2
°C/W
40
°C/W
(1)
The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch
× 3-inch (7,5-cm × 7,5-cm), multilayer board with 1-ounce
internal power and ground planes and 2-ounce copper traces on top and bottom of the board.
(2)
The JEDEC low-K (1s) board design used to derive this data was a 3-inch
× 3-inch (7,5-cm × 7,5-cm), two-layer board with 2-ounce
copper traces on top of the board.
2
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