AD9910 datasheet(6/60 Pages) AD

No de pièce	AD9910

Description	1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer

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Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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AD9910

Rev. 0 | Page 6 of 60

Parameter

Conditions/Comments

Min

Typ

Max

Unit

201.1 MHz Analog Output

±500 kHz

–87

dBc

±125 kHz

–87

dBc

±12.5 kHz

–91

dBc

301.1 MHz Analog Output

±500 kHz

–86

dBc

±125 kHz

–86

dBc

±12.5 kHz

–88

dBc

401.3 MHz Analog Output

±500 kHz

–84

dBc

±125 kHz

–84

dBc

±12.5 kHz

–85

dBc

SERIAL PORT TIMING CHARACTERISTICS

Maximum SCLK Frequency

70

Mbps

Minimum SCLK Clock Pulse Width

Low

4

ns

High

4

ns

Maximum SCLK Rise/Fall Time

2

ns

Minimum Data Setup Time to SCLK

5

ns

Minimum Data Hold Time to SCLK

0

ns

Maximum Data Valid Time in Read Mode

11

ns

I/O_UPDATE/PS0/PS1/PS2 TIMING

CHARACTERISTICS

Minimum Pulse Width

High

1

SYNC_CLK cycle

Minimum Setup Time to SYNC_CLK

2

ns

Minimum Hold Time to SYNC_CLK

0

ns

Tx_ENABLE and 16-BIT PARALLEL (DATA) BUS

TIMING

Maximum PDCLK Frequency

250

MHz

Tx_ENABLE/Data Setup Time (to PDCLK)

2

ns

Tx_ENABLE/Data Hold Time (to PDCLK)

1

ns

MISCELLANEOUS TIMING CHARACTERISTICS

Wake-Up Time2

1

ms

Fast Recovery

8

SYSCLK cycles

Full Sleep Mode

150

μs

Minimum Reset Pulse Width High

5

SYSCLK cycles3

DATA LATENCY (PIPE_LINE DELAY)

Data Latency, Single Tone or using Profiles

Frequency, Phase, Amplitude-to-DAC Output

Matched latency enabled and OSK

enabled

91

SYSCLK cycles

Frequency, Phase-to-DAC Output

Matched latency enabled and OSK

disabled

79

SYSCLK cycles

Matched latency disabled

79

SYSCLK cycles

Amplitude-to-DAC Output

Matched latency disabled

47

SYSCLK cycles

Data Latency using RAM Mode

Frequency, Phase-to-DAC Output

Matched latency enabled/disabled

94

SYSCLK cycles

Amplitude-to-DAC Output

Matched latency enabled

106

SYSCLK cycles

Matched latency disabled

58

SYSCLK cycles

Data Latency, Sweep Mode

Frequency, Phase-to-DAC Output

Matched latency enabled/disabled

91

SYSCLK cycles

Amplitude-to-DAC Output

Matched latency enabled

91

SYSCLK cycles

Matched latency disabled

47

SYSCLK cycles

Data Latency, 16-Bit Input Modulation Mode

Frequency, Phase-to-DAC Output

Matched latency enabled

103

SYSCLK cycles

Matched latency disabled

91

SYSCLK cycles

Numéro de pièce similaire - AD9910

Fabricant	No de pièce	Fiches technique	Description
Analog Devices	AD9910	488Kb / 13P	1 GSPS 14-Bit, 3.3V CMOS Direct Digital Synthesizer Rev. PrD
	AD9910	390Kb / 3P	Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers REV. A
	AD9910	1Mb / 64P	CMOS Direct Digital Synthesizer
	AD9910BSVZ	1Mb / 64P	CMOS Direct Digital Synthesizer
	AD9910BSVZ-REEL	1Mb / 64P	CMOS Direct Digital Synthesizer

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Description similaire - AD9910

Fabricant	No de pièce	Fiches technique	Description
Analog Devices	AD9910	488Kb / 13P	1 GSPS 14-Bit, 3.3V CMOS Direct Digital Synthesizer Rev. PrD
	AD9912BCPZ	649Kb / 40P	1 GSPS Direct Digital Synthesizer with 14-Bit DAC Rev. F
	AD9912	113Kb / 3P	1 GSPS Direct Digital Synthesizer w/ 14-bit DAC Rev. F
	AD9912ABCPZ	649Kb / 40P	1 GSPS Direct Digital Synthesizer with 14-Bit DAC Rev. F
	AD9858BSVZ	838Kb / 32P	1 GSPS Direct Digital Synthesizer REV. C
	AD9858	1Mb / 32P	1 GSPS Direct Digital Synthesizer REV. A
	AD9858	838Kb / 32P	1 GSPS Direct Digital Synthesizer REV. C
	AD9953	648Kb / 32P	400MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
	AD9954	742Kb / 40P	400MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
	AD9953YSVZ	574Kb / 32P	400 MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer REV. A

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