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TR8100 Fiches technique(PDF) 5 Page - RF Monolithics, Inc |
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TR8100 Fiches technique(HTML) 5 Page - RF Monolithics, Inc |
5 / 14 page RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-8148 E-mail: info@rfm.com Page 5 of 14 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 http://www.rfm.com ©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc. TR8100-021307 Figure 2 Receiver Chain The output of the SAW filter drives amplifier RFA1. This amplifier includes provisions for detecting the onset of saturation (AGC Set), and for switch- ing between 35 dB of gain and 5 dB of gain (Gain Select). AGC Set is an input to the AGC Control function, and Gain Select is the AGC Control function output. ON/OFF control to RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp Bias function. The output of RFA1 drives the SAW delay line, which has a nominal delay of 0.5 µs. The second amplifier, RFA2, provides 51 dB of gain below saturation. The output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The onset of saturation in each section of RFA2 is detected and summed to provide a logarithmic response. This is added to the output of the full- wave detector to produce an overall detector response that is square law for low signal levels, and transitions into a log response for high signal lev- els. This combination provides excellent threshold sensitivity and more than 70 dB of detector dynamic range. In combination with the 30 dB of AGC range in RFA1, more than 100 dB of receiver dynamic range is achieved. The detector output drives a gyrator filter. The filter provides a three-pole, 0.05 degree equiripple low-pass response with excellent group delay flat- ness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an external resistor. The filter is followed by a base-band amplifier which boosts the detected signal to the BBOUT pin with the receiver RF amplifiers operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 450 mV. The detected signal is riding on a 1.5 Vdc level that varies somewhat with supply voltage, temperature, etc. BBOUT is coupled to the CMPIN pin, or to an external data recovery process (DSP), by a series capacitor. The correct value of the series capacitor depends on data rate, data run length, and other factors as dis- cussed in the ASH Transceiver Designer’s Guide. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and to CMPIN by sepa- rate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. Data Slicers The CMPIN pin drives two data slicers, which convert the analog signal from BBOUT back into a digital stream. The best data slicer configuration depends on the system operating parameters. Data slicer DS1 is a capac- itively-coupled comparator with provisions for an adjustable threshold. DS1 provides the best performance at low signal-to-noise conditions. The threshold, or squelch, offsets the comparator’s slicing level from 0 to 90 mV, and is set with a resistor between the RREF and THLD1 pins. This threshold allows a trade-off between receiver sensitivity and output noise density in the no-signal condition. For best sensitivity, the threshold is set to zero but a minimum of 9 mv should be used for proper AGC action. In this case, noise is output continuously when no signal is present. This, in turn, requires the circuit being driven by the RXDATA pin to be able to pro- cess noise (and signals) continuously. This can be a problem if RXDATA is driving a circuit that must sleep when data is not present to conserve power, or when it its necessary to minimize false interrupts to a multitasking processor. In this case, noise can be greatly reduced by increasing the threshold level, but at the expense of sensitivity. The best 3 dB bandwidth for the low-pass filter is also affected by the threshold level setting of DS1. The bandwidth must be increased as the threshold is increased to minimize data pulse-width variations with sig- nal amplitude. 3G ASH Transceiver Block Diagram RFA1 RFA2 TXA1 TXA2 SAW Delay Line SAW CR Filter Log Antenna RFIO ESD Choke Detector Low-Pass Filter BB AGC Control Peak Detector Local Oscillator, Pulse Generator & RF Amp Bias LPFADJ RXDATA CN TRL1 CN TRL0 R REF THLD2 THLD1 Gain Select AGC Set AGC Reset Threshold Control BBOUT DS2 DS1 AND dB Below Peak Thld Ref Thld PKDET Ref AGC C BBO C PKD R LPF R TH2 R TH1 R TXM 20 8 17 18 14 15 9 56 4 7 13 11 12 VCC1: Pin 2 VCC3: Pin 3 VCC2: Pin 16 GND1: Pin 1 GND2: Pin 10 TX MOD 19 CN FGR X X Data/Clock Recovery RXDCLK Temperature Compensated Master Oscillator Baud Rate Selection Power Down Control Programming and Control |
Numéro de pièce similaire - TR8100 |
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Description similaire - TR8100 |
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