KM416S8030BN datasheet(4/9 Pages) SAMSUNG

No de pièce	KM416S8030BN

Description	128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

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Fabricant	SAMSUNG [Samsung semiconductor]

Site Internet	http://www.samsung.com/Products/Semiconductor

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KM416S8030BN

Rev. 0.1 Aug. 1999

CMOS SDRAM

Preliminary

shrink-TSOP

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

N.C/RFU

UDQM

CLK

CKE

N.C

A11

A9

A8

A7

A6

A5

A4

VSS

PIN FUNCTION DESCRIPTION

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

CS

Chip select

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA8

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

L(U)DQM

Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ 15

Data input/output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

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PIN CONFIGURATION (Top view)

54Pin sTSOP

(400mil x 441mil)

(0.4 mm Pin pitch)

Numéro de pièce similaire - KM416S8030BN

Fabricant	No de pièce	Fiches technique	Description
Samsung semiconductor	KM416S8030B	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030BT-G/F10	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030BT-G/F8	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030BT-G/FA	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030BT-G/FH	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

More results

Description similaire - KM416S8030BN

Fabricant	No de pièce	Fiches technique	Description
Samsung semiconductor	K4S281632B	108Kb / 10P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632M	87Kb / 10P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030B	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632C	47Kb / 9P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632D	112Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632C	112Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030	116Kb / 10P	2M x 16Bit x 4 Banks Synchronous DRAM
	K4S561632A	127Kb / 10P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
	K4S561632D-TC75000	64Kb / 11P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
	K4S561632B	131Kb / 11P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

More results

KM416S8030BN Fiches technique(PDF) 4 Page - Samsung semiconductor

KM416S8030BN Fiches technique(HTML) 4 Page - Samsung semiconductor

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