Si5326

10

Confidential Rev. 0.2

23

SDA_SDO

I/O

LVCMOS

Serial Data.

tional serial data port.

In SPI control mode (CMODE = 1), this pin functions as the serial

data output.

25

24

A1

A0

ILVCMOS

Serial Port Address.

ware controlled address bits.

In SPI control mode (CMODE = 1), these pins are ignored.

26

A2_SS

ILVCMOS

Serial Port Address/Slave Select.

controlled address bit.

In SPI control mode (CMODE = 1), this pin functions as the slave

select input.

27

SDI

I

LVCMOS

Serial Data In.

In SPI control mode (CMODE = 1), this pin functions as the serial

data input.

29

28

CKOUT1–

CKOUT1+

OMulti

Output Clock 1.

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by SFOUT1_REG

register bits. Output is differential for LVPECL, LVDS, and CML

compatible modes. For CMOS format, both output pins drive iden-

tical single-ended clock outputs.

34

35

CKOUT2–

CKOUT2+

OMulti

Output Clock 2.

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by SFOUT2_REG

register bits. Output is differential for LVPECL, LVDS, and CML

compatible modes. For CMOS format, both output pins drive iden-

tical single-ended clock outputs.

36

CMODE

I

LVCMOS

Control Mode.

1 = SPI Control Mode

GND PAD

GND

GND

Supply

Ground Pad.

The ground pad must provide a low thermal and electrical

impedance to a ground plane.

Pin #

Pin Name

I/O

Signal Level

Description

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map.