Philips Semiconductors

Product data

PCK2057

2001 Jun 12

4

11

0

1

0

0

1

su01394

R/W

1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only

the system.

The following address was confirmed by Philips on 09/04/96.

A6

A5

A4

A3

A2

A1

A0

R/W

11

01

00

10

indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the

R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.

2) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.

based on a 3.3 Volt supply.

4) Data Byte Format: Byte format is 8 Bits as described in the following appendices.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been

controller. The controller “writes” to the clock driver.

SW00911

1 bit

7 bits

1

1

8 bits

1

Start bit

Slave Address

R/W

DUMMY

DUMMY

Ack

Data Byte 1

Ack

Data Byte 2

Ack

Stop

Ack

Ack

1 bit

8 bits

1

1

8 bits

1

NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).

specification.

a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of

internal pull-ups on these pins of below 100 k

Ω is discouraged. Assume that the board designer will use a single external pull-up resistor for

each line and that these values are in the 5–6 k

mode device and is not required to support this feature.