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TPS61081DRCT Fiches technique(PDF) 2 Page - Texas Instruments |
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TPS61081DRCT Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 25 page www.ti.com L 1 10 SW Charge Pump 2 VIN EN SC Ramp Generator Oscillator FB 5 Clamp MUX BandGap 1.229V SS EN PWM Control Current Sensor Error Amplifer OVP Thermal Shutdown OVP ShortCircuit 9 OUT FSW 7 PGND 8 SC OVP 1.2MHz 600KHz 6 3 GND 4 + FB R1 R2 R3 C3 C2 Cs C1 L1 TPS61080 TPS61081 SLVS644B – FEBRUARY 2006 – REVISED JANUARY 2007 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. The inductor is connected between this pin and the SW pin. This pin connects to the source of the L 1 I isolation FET as well. Minimize trace area at this pin to reduce EMI. Input pin to the IC. It is the input to the boost regulator, and also powers the IC circuit. It is connected to VIN 2 I the drain of the isolation FET as well. Enable pin. When the voltage of this pin falls below enable threshold for more than 74ms, the IC turns off EN 6 I and consumes less than 2 µA current. GND 4 Signal ground of the IC Power ground of the IC. It is connected to the source of the PWM switch. This pin should be made very PGND 8 close to the output capacitor in layout. Voltage feedback pin for the output regulation. It is regulated to an internal reference voltage. An external FB 5 I voltage divider from the output to GND with the center tap connected to this pin programs the regulated voltage. This pin can also be connected to a low side current sense resistor to program current regulation. Output of the boost regulator. When the output voltage exceeds the 27V overvoltage protection (OVP) OUT 9 O threshold, the PWM switch turns off until Vout drops 0.7V below the overvoltage threshold. SW 10 I Switching node of the IC. Connect the inductor between this pin and the L pin. SS 3 I Soft start programming pin. A capacitor between the SS pin and GND pin programs soft start timing. Switching frequency selection pin. Logic high on the pin selects 1.2MHz, while logic low reduces the FSW 7 I frequency to 600KHz for better light load efficiency. The thermal pad should be soldered to the analog ground. If possible, use thermal via to connect to Thermal Pad – ground plane for ideal power dissipation. FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback |
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