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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS40131RHBR Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS40131RHBR Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 46 page  www.ti.com RHB PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 15 16 BOOT1 OVSET VOUT GSNS DIFFO CS1 CSRT1 COMP BOOT2 SS UVLO BP5 AGND CS2 CSRT2 RT 14 1 2 3 4 5 6 7 8 TPS40131 SLVS635 – FEBRUARY 2007 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AGND 20 - Low noise ground connection to the device. Provides a bootstrapped supply for the high-side FET driver for PWM1, enabling the gate of the high-side BOOT1 1 I FET to be driven above the input supply rail. Connect a capacitor from this pin to SW1 pin and a Schottky diode from this pin to VIN5. Provides a bootstrapped supply for the high-side FET driver for PWM2, enabling the gate of the high-side BOOT2 24 I FET to be driven above the input supply rail. Connect a capacitor from this pin to SW2 pin and a Schottky diode from this pin to VIN5. Filtered input from the VIN5 pin. A 10- Ω resistor should be connected between VIN5 and BP5 and a BP5 21 O 1.0- µF ceramic capacitor should be connected from this pin to ground. Output of the LDO that powers the differential amplifer and the current sense amplifiers. The voltage is BP8 13 O approximately (VVDD -0.2 V) until the output regulates at approximately 7.5 V. Decouple this pin with a minimum capacitance of 1.0- µF to GND. COMP 8 O Output of the error amplifier. The voltage at this pin determines the duty cycle for the PWM. CS1 6 I These pins are used to sense the inductor phase current. Inductor current can be sensed with an external current sense resistor or by using an external R-C circuit and the inductor's DC resistance. The traces for these signals must be connected directly at the current sense element. See Layout Guidelines for more CS2 19 I information. CSRT1 7 O Return point of current sense voltage. The traces for these signals must be connected directly at the current sense element. See Layout Guidelines for more information. CSRT2 18 O Output of the differential amplifier. The voltage at this pin represents the true output voltage without IR DIFFO 5 O drops that result from high-current in the PCB traces. The VOUT and GSNS pins must be connected directly at the point of load where regulation is required. See Layout Guidelines for more information. This is the input to the non-inverting input of the Error Amplifier. This pin is normally connected to the +EA 10 I VREF pin and is the voltage that the feedback loop regulates to. A logic high signal on this input enables the controller operation. A pulsing signal to this pin synchronizes EN/SYNC 14 I the rising edge of SW to the falling edge of an external clock source. Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal FB 11 I reference level of 700 mV. This pin is also used for the PGOOD and undervoltage comparators. GSNS 4 I Inverting input of the differential amplifier. This pin should be connected to ground at the point of load. Gate drive output for the high-side N-channel MOSFET switch for PWM1. Output is referenced to SW1 HDRV1 32 O and is bootstrapped for enhancement of the high-side switch. 7 Submit Documentation Feedback |
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