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CDCE421RGETG4 Fiches technique(PDF) 11 Page - Texas Instruments |
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CDCE421RGETG4 Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 30 page www.ti.com PACKAGE (DIE) 10 11 12 13 14 15 16 17 2 6 PAD1 TI TEST ONLY GND SIGNALS 9 8 7 5 3 4 M0070-01 v cc PAD DESCRIPTION CDCE421 SCAS842 – APRIL 2007 The CDCE421 is available in die form or in a QFN 24-pin package. The die version pad locations and numbers are shown in Figure 5. Figure 5. Pinout of the CDCE421 Die Table 2 shows the pin description for the CDCE421 die. Table 2. Pad Description of CDCE421 (See Appendix B for More Information) TERMINAL ESD PAD NO. TYPE Description NAME Protection CE 1 O Y Chip enable CE = 1: enable the device and the outputs. CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z; in LVPECL mode, LVPECLP = LVPECLN = Hi-Z. OUTN 3 O Y High-speed negative differential LVPECL or LVDS outputs. (Outputs are enabled by CE and selected by the EEPROM configuration registers.) OUTP 6 O Y High-speed positive differential LVPECL or LVDS outputs. (Outputs are enabled by CE and selected by the EEPROM configuration registers.) SDATA 2 I Y Programming pin using TI proprietary interface protocol Test pins 7, 8, 11–13, Do not connect (TI Manufacturing test pins). 16, 17 VCC 9, 10 Power Y 3.3-V power supply VSS 4, 5 GND Y Ground XIN 1 14 I Y Connect XIN1 to one end of the crystal and XIN2 to the other end of the crystal. XIN 2 15 I N 11 Submit Documentation Feedback |
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